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I/O Design Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Location
Singapore, Singapore
Work type
fulltime
Source publication date
Original publication date not confirmed
Source closing date
Not supplied — check original advert

Job description from the source

**Company Overview** Broadcom Inc. is a global technology leader designing and supplying semiconductor and infrastructure software solutions for data center, networking, software, broadband, wireless, storage, and industrial markets. Visit www.broadcom.com for more information. **Job Summary** Broadcom’s Central Engineering Group seeks an experienced I/O Design Engineer to design and verify analog and mixed-signal ICs, contributing to advanced AI programs and collaborating within a world-class engineering team. **Responsibilities** * Design CMOS I/O circuits, high-precision bandgap references, operational amplifiers, comparators, and power-on-reset circuits to meet performance targets * Run simulations to validate AC/DC performance, signal integrity, jitter, and power consumption for circuit reliability * Perform transistor reliability and electromigration (EMIR) analysis to ensure device robustness * Collaborate with layout teams to oversee physical design and verify adherence to specifications * Develop Verilog, Synopsys Liberty, and IBIS models to support design integration and verification * Create and maintain comprehensive technical documentation including datasheets, application notes, and integration guides for internal and customer use * Support chip-level integration and silicon bring-up activities for test chips and customer products to ensure successful deployment **Required competencies and certifications** * Master’s or PhD degree in Electrical Engineering * Minimum 6 years of experience in I/O or analog circuit design * Proficient in Cadence Virtuoso schematic capture, layout, and SPICE/Spectre circuit simulation tools * Strong understanding of I/O protocols such as GPIO, I2C, I3C, eMMC, RGMII, and SPMI * Knowledge of ESD, EMI, and signal integrity principles * Experience with advanced CMOS FinFET and GAA process nodes, including technology features, limitations, and power-performance-area tradeoffs

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