Digital Design Engineer

**Digital Design Engineer** =========================== Experience Level: Professional Job Type: Regular Location: Chandler, AZ, US, 85226 Requisition ID: 10856 Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems\-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high\-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery\-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. DUTIES: Verilog design of digital control logic for mobile phone LNAs, TX controllers and switches. This specifically involves working with and/or having knowledge of design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus are required; RTL\-to\-GDS flow, area optimization, and DRC/LVS error resolution; digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL; Verilog digital design and verification and understanding of Verilog/System Verilog syntax; understanding of verification test benches, clocking and auto\-checking; performing verification on the Verilog code using simulation tools; and Python scripting and other scripting languages. Additionally, responsibilities include the creation of test benches and verification through simulation of the above designs using Xcelium, Verilog and Python automation; constraint creation and synthesis of mobile phone digital circuit designs with Cadence Genus, Conformal; and physical design and timing closure of mobile phone digital circuit designs with Cadence Innovus. Further, the responsibilities include script automation development with Python to aid in the design of Qorvo’s mobile designs. Hybrid: 3 days in the office and 2 work from within reasonable commuting distance from the office. MINIMUM REQUIREMENTS: Master’s degree in Electrical Engineering and 6 months of experience, an internship, co\-op, or 6 graduate credit hours to involve knowledge of: (1\) design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus are required; RTL\-to\-GDS flow, area optimization, and DRC/LVS error resolution; (3\) digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL; (4\) Verilog digital design and verification and understanding of Verilog/System Verilog syntax; (5\) understanding of verification test benches, clocking and auto\-checking; (6\) performing verification on the Verilog code using simulation tools; and (7\) Python scripting and other scripting languages. Hybrid: 3 days in the office and 2 work from within reasonable commuting distance from the office. ***This position is not eligible for visa sponsorship by the Company.*** MAKE A DIFFERENCE AT QORVO We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us. We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability. Qorvo is an E\-Verify Employer. For more information, please see the Right to Work and E\-Verify Participation posters.